The present invention relates to integrated content addressable memory (CAM) arrays, and in particular to low-power CAM arrays.
Conventional random access memory (RAM) arrays include RAM cells (e.g., static RAM (SRAM) cells, dynamic RAM (DRAM) cells, and non-volatile RAM (NVRAM) cells) that are arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells within the RAM array. A data word is typically written into a RAM array by applying physical address signals to the RAM array input terminals to access a particular group of RAM cells, and applying data word signals to the RAM array input terminals that are written into the accessed group of RAM cells. During a subsequent read operation, the physical address of the group of RAM cells is applied to the RAM array input terminals, causing the RAM array to output the data word stored therein. Groups of data words are typically written to or read from the RAM array one word at a time. Therefore, a relatively small portion of the entire RAM array circuitry is activated at one time to perform each data word read/write operation, so a relatively small amount of switching noise occurs within the RAM array, and the amount of power required to operate the RAM array is relatively small.
In contrast to RAM arrays, content addressable memory (CAM) arrays store data values that are accessed in response to their content, rather than by a physical address. Specifically, during compare (search) operations, a CAM array receives a searched-for data value that is simultaneously compared with all of the data words stored in the CAM array. In response to each searched-for data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value. Therefore, large amounts of data can be searched simultaneously, so CAM arrays are often much faster than RAM arrays in performing certain functions, such as search engines.
While CAM arrays are faster than RAM arrays in performing search functions, they consume significantly more power and generate significantly more switching noise than RAM arrays. In particular, in contrast to RAM arrays in which only a small portion of the total circuitry is accessed during each read and write operation, significantly more power is needed (and noise is generated) in a CAM array because, during compare (search) operations, all of the CAM cells are accessed simultaneously, and those CAM cells that do not match the applied search data value typically switch an associated match line from a high voltage to a low voltage. Switching the large number of match lines at one time consumes a significant amount of power.
To reduce the total power consumed by CAM arrays, there is a trend toward producing CAM arrays that operate on low system (operating) voltages. To facilitate lower system voltages, the integrated circuit (IC) fabrication technologies selected to produce such CAM arrays utilize smaller and smaller feature sizes. In general, the smaller the feature size of an IC, the lower the operating voltage that is used to operate the IC. However, when IC feature sizes and operating voltages are reduced too much, the amount of charge stored at each node within the CAM array becomes so small that a xe2x80x9csoft errorxe2x80x9d problem arises, which is discussed below with reference to FIG. 1.
FIG. 1 is a simplified cross sectional view showing an exemplary IC feature (e.g., a drain junction utilized to form an n-type transistor) that comprises an n-type diffusion (node) 50 formed in p-type well (P-WELL) 51, which in turn is formed in a p-type substrate 52. Dashed line capacitor 53 represents the capacitance of node 50, and indicates that node 50 stores apositive charge.
As indicated in FIG. 1, if an energetic particle, such as an alpha particle (xcex1), from the environment or surrounding structure strikes the n-type diffusion of node 50, then electrons (e) and holes (h) will be generated within the underlying body of semiconductor material (i.e., in p-well 51 or p-type substrate 52). These free electrons and holes travel to the node 50 and p-well 51/p-substrate 52, respectively, thereby creating a short circuit current that reduces the charge stored at node 50. If the energy of the alpha particle is sufficiently strong, or if the capacitance 53 is too small, then node 50 can be effectively discharged. When node 50 forms a drain in an SRAM cell and the charge perturbation is sufficiently large, the stored logic state of the SRAM cell may be reversed (e.g., the SRAM cell can be flipped from storing a logic xe2x80x9c1xe2x80x9d to a logic xe2x80x9c0xe2x80x9d) . This radiation-produced data change is commonly referred to as a xe2x80x9csoft errorxe2x80x9d because the error is not due to a hardware defect and the cell will operate normally thereafter (although it may contain erroneous data until rewritten).
Many approaches have been proposed for dealing with soft errors, such as increased cell capacitance or Ioperating voltage, and error detection schemes (such as using one or more parity bits). While these proposed approaches are suitable for standard RAM arrays, they are less desirable in CAM arrays. As pointed out above, CAM arrays inherently consume more power than RAM arrays. Therefore, while increased cell size and/or operating voltage can be tolerated in a RAM array, such solutions are less desirable in a CAM arrays. Moreover, adding error detection schemes to CAM arrays increase the size (and, hence, the cost) of the CAM arrays, and further increase power consumption.
Accordingly, what is needed is a CAM circuit that addresses the soft error problem associated with the low power CAM operating environment without greatly increasing the cost and power consumption of the CAM circuit.
The present invention is directed to a CAM circuit that addresses the soft error problem associated with the low power CAM operating environment by utilizing multiple operating voltages including a relatively high memory operating voltage to drive the memory portion of each CAM cell, and a relatively low logic operating voltage to drive (control) the logic portion of each CAM cell. Because the memory cell of each CAM cell in the CAM circuit is accessed relatively independently during, for example, write operations, the use of a relatively high operating voltage to store data values in these memory cells increases the amount of stored charge, thereby reducing the chance of xe2x80x9csoft errorxe2x80x9d discharge, without significantly increasing power consumption of the overall CAM circuit. Further, because all of the logic portions (e.g., the comparators, match lines, and data lines) and of the CAM circuit are accessed at the same time during compare operations, the use of a relatively low operating voltage to drive the logic portions reduces power consumption when compared with CAM circuits utilizing a single, relatively high voltage to drive both memory and logic portions.
In accordance with a first specific embodiment of the present invention, the memory portion of each CAM cell includes an SRAM cell controlled by an associated word line to store a data value transmitted on complementary bit lines, and the logic portion of each CAM cell includes a comparator that compares the data values stored by the SPAM cell with an applied data value transmitted on complementary data lines, and discharges a match line when the stored data value differs from the applied data value. In this first embodiment, a storage node of the SRAM cell is selectively coupled to a relatively high memory operating voltage (e.g., 2.5 Volts) during write operations (e.g., when the SRAM cell stores a logic xe2x80x9c1xe2x80x9d data value), thereby providing a relatively high stored charge that resists soft error discharge. In contrast, the complementary data lines, match line, and an optional low match line of the logic portion are driven using a relatively low logic operating voltage (e.g., 1.2 to 1.5 Volts). The complementary bit lines and word line used to control the SRAM cell during write operations are controlled either using the relatively high memory operating voltage, or the relatively low logic operating voltage. With this arrangement, separate control circuits are utilized to drive the bit lines and data lines, thereby facilitating relatively fast CAM operations.
In accordance with a second embodiment of the present invention, each CAM cell includes an SRAM (memory) cell that is controlled to store a data value transmitted on complementary bit/data lines during write operations, and a comparator that compares the data values stored by the SRAM cell with an applied data value transmitted on the complementary bit/data lines during a compare operation. In one operating mode of the second embodiment, a control circuit is provided that applies a relatively high memory operating voltage (e.g., 2.5 Volts) to the complementary bit/data lines during the write operations, and applies a relatively low logic operating voltage (e.g., 1.2 to 1.5 Volts) during the compare operations. In another operating mode, the control circuit is provided that applies the relatively low logic operating voltage during both write and compare operations. In both operating modes, the relatively high operating voltage is used to drive the memory cell(s) of each CAM cell such that the stored data value resists soft error discharge. Similarly, as in the first embodiment, the match line is controlled using the relatively low logic operating voltage.
In accordance with a third embodiment of the present invention, the memory portion of each CAM cell includes a DRAM cell controlled by an associated word line to store a data value transmitted on a bit line, and the logic portion of each CAM cell includes a comparator similar to that of the first embodiment. In this third embodiment, the bit line and word line used to operate the DRAM cell are driven using a relatively high memory operating voltage (e.g., 2.5 Volts), thereby causing the DRAM cell to selectively store a relatively high voltage. As in the previous embodiments, the complementary data lines, match line, and an optional low match line of the logic portion are driven using a relatively low logic operating voltage (e.g., 1.2 to 1.5 Volts) to minimize power consumption.
The present invention will be more fully understood in view of the following description and drawings.